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Vulnerability Details :

CVE-2025-0647

Summary
Assigner-Arm
Assigner Org ID-56a131ea-b967-4a0d-a41e-5f3549952846
Published At-14 Jan, 2026 | 10:58
Updated At-20 Jan, 2026 | 15:21
Rejected At-
Credits

In certain Arm CPUs, a CPP RCTX instruction executed on one Processing Element (PE) may inhibit TLB invalidation when a TLBI is issued to the PE, either by the same PE or another PE in the shareability domain. In this case, the PE may retain stale TLB entries which should have been invalidated by the TLBI.

Vendors
-
Not available
Products
-
Metrics (CVSS)
VersionBase scoreBase severityVector
Weaknesses
Attack Patterns
Solution/Workaround
References
HyperlinkResource Type
EPSS History
Score
Latest Score
-
N/A
No data available for selected date range
Percentile
Latest Percentile
-
N/A
No data available for selected date range
Stakeholder-Specific Vulnerability Categorization (SSVC)
▼Common Vulnerabilities and Exposures (CVE)
cve.org
Assigner:Arm
Assigner Org ID:56a131ea-b967-4a0d-a41e-5f3549952846
Published At:14 Jan, 2026 | 10:58
Updated At:20 Jan, 2026 | 15:21
Rejected At:
▼CVE Numbering Authority (CNA)

In certain Arm CPUs, a CPP RCTX instruction executed on one Processing Element (PE) may inhibit TLB invalidation when a TLBI is issued to the PE, either by the same PE or another PE in the shareability domain. In this case, the PE may retain stale TLB entries which should have been invalidated by the TLBI.

Affected Products
Vendor
Arm LimitedArm
Product
Neoverse-N2
Default Status
unaffected
Versions
Affected
  • 0
Vendor
Arm LimitedArm
Product
Neoverse-V3AE
Default Status
unaffected
Versions
Affected
  • 0
Vendor
Arm LimitedArm
Product
Neoverse-V3
Default Status
unaffected
Versions
Affected
  • 0
Vendor
Arm LimitedArm
Product
Neoverse-V2
Default Status
unaffected
Versions
Affected
  • 0
Vendor
Arm LimitedArm
Product
Cortex-X925
Default Status
unaffected
Versions
Affected
  • 0
Vendor
Arm LimitedArm
Product
Cortex-X4
Default Status
unaffected
Versions
Affected
  • 0
Vendor
Arm LimitedArm
Product
Cortex-X3
Default Status
unaffected
Versions
Affected
  • 0
Vendor
Arm LimitedArm
Product
Cortex-X2
Default Status
unaffected
Versions
Affected
  • 0
Vendor
Arm LimitedArm
Product
Cortex-A710
Default Status
unaffected
Versions
Affected
  • 0
Vendor
Arm LimitedArm
Product
C1-Premium
Default Status
unaffected
Versions
Affected
  • 0
Vendor
Arm LimitedArm
Product
C1-Ultra
Default Status
unaffected
Versions
Affected
  • 0
Problem Types
TypeCWE IDDescription
CWECWE-226CWE-226 Sensitive Information in Resource Not Removed Before Reuse
Type: CWE
CWE ID: CWE-226
Description: CWE-226 Sensitive Information in Resource Not Removed Before Reuse
Metrics
VersionBase scoreBase severityVector
Metrics Other Info
Impacts
CAPEC IDDescription
Solutions

Configurations

Workarounds

Exploits

Credits

Timeline
EventDate
Replaced By

Rejected Reason

References
HyperlinkResource
https://developer.arm.com/documentation/111546
N/A
Hyperlink: https://developer.arm.com/documentation/111546
Resource: N/A
▼Authorized Data Publishers (ADP)
CISA ADP Vulnrichment
Affected Products
Metrics
VersionBase scoreBase severityVector
3.17.9HIGH
CVSS:3.1/AV:L/AC:L/PR:H/UI:N/S:C/C:H/I:H/A:N
Version: 3.1
Base score: 7.9
Base severity: HIGH
Vector:
CVSS:3.1/AV:L/AC:L/PR:H/UI:N/S:C/C:H/I:H/A:N
Metrics Other Info
Impacts
CAPEC IDDescription
Solutions

Configurations

Workarounds

Exploits

Credits

Timeline
EventDate
Replaced By

Rejected Reason

References
HyperlinkResource
https://graph.volerion.com/view?ID=CVE-2025-0647
third-party-advisory
Hyperlink: https://graph.volerion.com/view?ID=CVE-2025-0647
Resource:
third-party-advisory
Information is not available yet
▼National Vulnerability Database (NVD)
nvd.nist.gov
Source:arm-security@arm.com
Published At:14 Jan, 2026 | 11:15
Updated At:26 Jan, 2026 | 19:40

In certain Arm CPUs, a CPP RCTX instruction executed on one Processing Element (PE) may inhibit TLB invalidation when a TLBI is issued to the PE, either by the same PE or another PE in the shareability domain. In this case, the PE may retain stale TLB entries which should have been invalidated by the TLBI.

CISA Catalog
Date AddedDue DateVulnerability NameRequired Action
N/A
Date Added: N/A
Due Date: N/A
Vulnerability Name: N/A
Required Action: N/A
Metrics
TypeVersionBase scoreBase severityVector
Secondary3.17.9HIGH
CVSS:3.1/AV:L/AC:L/PR:H/UI:N/S:C/C:H/I:H/A:N
Type: Secondary
Version: 3.1
Base score: 7.9
Base severity: HIGH
Vector:
CVSS:3.1/AV:L/AC:L/PR:H/UI:N/S:C/C:H/I:H/A:N
CPE Matches

Arm Limited
arm
>>c1-ultra_firmware>>-
cpe:2.3:o:arm:c1-ultra_firmware:-:*:*:*:*:*:*:*
Arm Limited
arm
>>c1-ultra>>-
cpe:2.3:h:arm:c1-ultra:-:*:*:*:*:*:*:*
Arm Limited
arm
>>c1-premium_firmware>>-
cpe:2.3:o:arm:c1-premium_firmware:-:*:*:*:*:*:*:*
Arm Limited
arm
>>c1-premium>>-
cpe:2.3:h:arm:c1-premium:-:*:*:*:*:*:*:*
Arm Limited
arm
>>cortex-a710_firmware>>-
cpe:2.3:o:arm:cortex-a710_firmware:-:*:*:*:*:*:*:*
Arm Limited
arm
>>cortex-a710>>-
cpe:2.3:h:arm:cortex-a710:-:*:*:*:*:*:*:*
Arm Limited
arm
>>cortex-x2_firmware>>-
cpe:2.3:o:arm:cortex-x2_firmware:-:*:*:*:*:*:*:*
Arm Limited
arm
>>cortex-x2>>-
cpe:2.3:h:arm:cortex-x2:-:*:*:*:*:*:*:*
Arm Limited
arm
>>cortex-x3_firmware>>-
cpe:2.3:o:arm:cortex-x3_firmware:-:*:*:*:*:*:*:*
Arm Limited
arm
>>cortex-x3>>-
cpe:2.3:h:arm:cortex-x3:-:*:*:*:*:*:*:*
Arm Limited
arm
>>cortex-x4_firmware>>-
cpe:2.3:o:arm:cortex-x4_firmware:-:*:*:*:*:*:*:*
Arm Limited
arm
>>cortex-x4>>-
cpe:2.3:h:arm:cortex-x4:-:*:*:*:*:*:*:*
Arm Limited
arm
>>cortex-x925_firmware>>-
cpe:2.3:o:arm:cortex-x925_firmware:-:*:*:*:*:*:*:*
Arm Limited
arm
>>cortex-x925>>-
cpe:2.3:h:arm:cortex-x925:-:*:*:*:*:*:*:*
Arm Limited
arm
>>neoverse-v2_firmware>>-
cpe:2.3:o:arm:neoverse-v2_firmware:-:*:*:*:*:*:*:*
Arm Limited
arm
>>neoverse-v2>>-
cpe:2.3:h:arm:neoverse-v2:-:*:*:*:*:*:*:*
Arm Limited
arm
>>neoverse-v3_firmware>>-
cpe:2.3:o:arm:neoverse-v3_firmware:-:*:*:*:*:*:*:*
Arm Limited
arm
>>neoverse-v3>>-
cpe:2.3:h:arm:neoverse-v3:-:*:*:*:*:*:*:*
Arm Limited
arm
>>neoverse-v3ae_firmware>>-
cpe:2.3:o:arm:neoverse-v3ae_firmware:-:*:*:*:*:*:*:*
Arm Limited
arm
>>neoverse-v3ae>>-
cpe:2.3:h:arm:neoverse-v3ae:-:*:*:*:*:*:*:*
Arm Limited
arm
>>neoverse-n2_firmware>>-
cpe:2.3:o:arm:neoverse-n2_firmware:-:*:*:*:*:*:*:*
Arm Limited
arm
>>neoverse-n2>>-
cpe:2.3:h:arm:neoverse-n2:-:*:*:*:*:*:*:*
Weaknesses
CWE IDTypeSource
CWE-226Secondaryarm-security@arm.com
CWE ID: CWE-226
Type: Secondary
Source: arm-security@arm.com
Evaluator Description

Evaluator Impact

Evaluator Solution

Vendor Statements

References
HyperlinkSourceResource
https://developer.arm.com/documentation/111546arm-security@arm.com
Vendor Advisory
https://graph.volerion.com/view?ID=CVE-2025-0647134c704f-9b21-4f2e-91b3-4a467353bcc0
Third Party Advisory
Hyperlink: https://developer.arm.com/documentation/111546
Source: arm-security@arm.com
Resource:
Vendor Advisory
Hyperlink: https://graph.volerion.com/view?ID=CVE-2025-0647
Source: 134c704f-9b21-4f2e-91b3-4a467353bcc0
Resource:
Third Party Advisory

Change History

0
Information is not available yet

Similar CVEs

1Records found

CVE-2024-7883
Matching Score-6
Assigner-Arm Limited
ShareView Details
Matching Score-6
Assigner-Arm Limited
CVSS Score-3.7||LOW
EPSS-0.37% / 58.75%
||
7 Day CHG~0.00%
Published-31 Oct, 2024 | 17:01
Updated-23 Dec, 2025 | 15:30
Rejected-Not Available
Known To Be Used In Ransomware Campaigns?-Not Available
KEV Added-Not Available
KEV Action Due Date-Not Available
CMSE secure state may leak from stack to floating-point registers

When using Arm Cortex-M Security Extensions (CMSE), Secure stack contents can be leaked to Non-secure state via floating-point registers when a Secure to Non-secure function call is made that returns a floating-point value and when this is the first use of floating-point since entering Secure state. This allows an attacker to read a limited quantity of Secure stack contents with an impact on confidentiality. This issue is specific to code generated using LLVM-based compilers.

Action-Not Available
Vendor-Arm Limited
Product-clangarm_compiler_for_embedded_fusaarm_compiler_for_embeddedarm_compiler_for_functional_safetyArm Compiler for Embedded FuSa 6.21CLangArm Compiler for Functional Safety 6.6Arm Compiler for EmbeddedArm Compiler for Embedded FuSa 6.16LTS
CWE ID-CWE-226
Sensitive Information in Resource Not Removed Before Reuse
Details not found